Learn PIC Assembly Language Part - 2

Instruction Set :

The PIC 18F452 has got 75 instructions, while the enhanced MCUs has got 83 instructions. Further 8 instructions are added for architectural and compiler optimisations.

Most instructions are a single program memory word (16-bits), but there are three instructions that require program memory locations. Each single word instruction is a 16-bit word divided into an OPCODE, which specifies the instruction typeand one or more operands, which further specify the operation of the instruction.

The instruction set is highly orthogonal and is grouped into four basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

• Control operations

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator 'f' specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located.

The literal instructions may use some of the following operands:

1. A literal value to be loaded into a file register (specified by ‘k’)

2. The desired FSR register to load the literal value into (specified by ‘f’)

2. No operand required (specified by ‘—’)

The control instructions may use some of the following operands:

• A program memory address (specified by ‘n’)

• The mode of the Call or Return instructions (specified by ‘s’)

• The mode of the Table Read and Table Write instructions (specified by ‘m’)

• No operand required (specified by ‘—’)

Byte Oriented File Register Operations :

1. ADDWF f, d, a

Description : ADD ing working register WREG with file register f. If d = 0, the result is stored in the file register WREG, or if d = 1 , then result is stored the file register f itself. The ‘a’ = 0 represents access bank, whereas a = 1, indicates bank is specified by BSR.

Ex : ADDWF 0x04,0,0

This instruction adds the value at the location 0x04 H with the contents of WREG and put the result back in WREG. Since a = 0, no banking is required and access RAM is used.

The status bits affected are C, DC, OV, Z, and N

2. ADDWFC f, d, a

Description : ADD ing working register WREG with file register f along with carry. If d = 0, the result is stored in the file register WREG, or if d = 1 , then result is stored the file register f itself. The ‘a’ = 0 represents access bank, whereas a = 1, indicates bank is specified by BSR.

Ex : ADDWFC 0x05,0,0

This instruction adds the value at the location 0x05 H with the contents of WREG along with carry and put the result back in WREG. Since a = 0, no banking is required and access RAM is used.

The status bits affected are C, DC, OV, Z, and N

3. ANDWF f, d, a

Description : AND ing working register WREG with file register f. If d = 0, the result is stored in the file register WREG, or if d = 1 , then result is stored the file register f itself. The ‘a’ = 0 represents access bank, whereas a = 1, indicates bank is specified by BSR.

Ex : ANDWF 0x05,0,0

This instruction ANDs the value at the location 0x05 H with the contents of WREG and put the result back in WREG. Since a = 0, no banking is required and access RAM is used.

The status bits affected are Z and N

4. CLRF f, a

Description : Clears the file register f. Value 0 will be loaded in the file register f.

Ex : CLRF 0x03,0

The value at the location 0x03 will be zero. And the carry flag will be affected.

5. COMF f, d, a

Description : Complements the given file register f

Ex1. COMF 0x99, 0,0

This will complement the value at the loctaion 0x99 and put the result back in WREG.

Ex2. COMF 0x99,1,0

This will complement the value at the loctaion 0x99 and put the result back in register file f.

The status bits affected are Z and N


6. CPFSEQ f,a

Description : Compares the file register f with WREG and skip the next instruction if it is equal. No flags are affected.


7. CPFSGT f,a

Description : Compares the file register f with WREG and skip the next instruction if it is greater. No flags are affected.

8. CPFSLT f,a

Description : Compares the file register f with WREG and skip the next instruction if it is lesser. No flags are affected.

9. DECF f, d, a

Description : Decrements the value at the file register f by one and stores the result in WREG or f itself accorcing to the value of d.

The flags affected are C, DC, OV, N and Z.

Ex. DECF 0x45, 0,0


This instruction decrements the value at the location 0x45H and put the value back in WREG as d = 0.

10. DECFSZ f,d a

Descirption : Decrements the value at the location f and skips the next instruction if the resulting value is zero.
No flags are affected by this instruction.

Ex. DECFSZ 0x56,0,0

This instruction decrements the value at f and skips the next instruction if its zero. The decremented value is stored at f only if the value of ‘d’ in the instruction is 1.

11. DECFSNZ f,d,a

Descirption : Decrements the value at the location f and skips the next instruction if the resulting value is not zero.
No flags are affected by this instruction.

Ex. DECFSNZ 0x56,0,0

This instruction decrements the value at f and skips the next instruction if its not zero. The decremented value is stored at f only if the value of ‘d’ in the instruction is 1.

12. INCF f,d,a

Description : Increments the value at the file register f by one and stores the result in WREG or f itself according to the value of d.

The flags affected are C, DC, OV, N and Z.

Ex. INCF 0x50, 0,0

This instruction increments the value at the location 0x50H and put the value back in WREG as d = 0.


13. INCFSZ f,d,a

Description: Increments the value at the location f and skips the next instruction if the resulting value is zero.
No flags are affected by this instruction.

Ex. INCFSZ 0x78,0,0

This instruction increments the value at f and skips the next instruction if its zero. The incremented value is stored at f only if the value of ‘d’ in the instruction is 1.

14. INCFSNZ f,d,a

Descirption : Increments the value at the location f and skips the next instruction if the resulting value is not zero.
No flags are affected by this instruction.

Ex. INCFSNZ 0x56,0,0

This instruction increments the value at f and skips the next instruction if its not zero. The incremented value is stored at f only if the value of ‘d’ in the instruction is 1.

15. IORWF f,d,a

Description : Inclusive OR with working register WREG. The result is put in WREG or ‘f’ itself according to the value of ‘d’. The flags affected are Z and N.
Ex. IORWF 0x11,0,0
This instruction performs inclusive OR with WREG and put the result back in WREG.

16. MOVF f,d,a

Description : Moves file register . The flags affected are Z and N. This instruction is only used to check the status of the flags Z and N

17. MOVFF fs, fd

Description : Moves the value at location fs ( source) to fd(destination). Anyone of the locations can be WREG. The fs or fd can be anywhere between 0x000 H and 0x FFF H. Ie Anywhere between 4096 location of data memory.

Ex. MOVFF 0x0127,0xF45

This instruction moves a byte of data from location 0x127 to location 0xF45. None of the flags are affected by this instruction.

18. MOVWF f, a

Description : Moves the value at working register WREG to file register ‘f’. None of the flags are affected by this instruction.

Ex. MOVWF 0x3C, 0

This instruction moves the value of WREG to location 0x3C.

19. MULWF f, a

Description : Multiplies working register WREG with f. An unsigned multiplication is performed between WREG and f. Neither overflow nor carry is generated in this operation. None of the flags are affected in this operation. The 16 – bit result is stored in registers PRODH and PRODL.

Ex. MULWF 0xD6,0

This instruction multiplies the value of WREG with value at the location 0xD6 and result is stored in the two registers PRODH and PRODL.

20. NEGF f,a

Description : Negates the value at f and stores at the same location. Negation is done using 2 s complement form. Its complements the value at ‘f’ and the add one to it. The resulting value is then put back to ‘f’. The flags affected are C, DC, OV, N and Z.

21. RLCF f,d,a

Description : Rotates the value at register file ‘f’ through carry by one position to the left. The flags affected are C , Z and N.

22. RLNCF f,d,a

Description : Rotates the value at register file ‘f’ without carry by one position to the left. The flags affected are Z and N.

23. RRCF f,d,a

Description : Rotates the value at register file ‘f’ with carry by one position to the right . The flags affected are C, Z and N.

24. RRNCF f,d,a

Description : Rotates the value at register file ‘f’ without carry by one position to the right. The flags affected are Z and N.

25. SETF f,a

Description : Set all the bits at the location given by register file ‘f’. None of the flags are affected by this instruction.

Ex. SETF 0x3A,0

This instruction sets all the bits of the location 0x3A H.

26. SUBFWB f,d,a

Description : Subtracts the value at register file ‘f’ from working register WREG with borrow. The flags affected are C, DC, OV, Z and N.

Ex. SUBFWB 0x45,0,0 ; Assume the value of WREG is 0x10 and value at 0x45H is 0x02

After executing this instruction the result is the difference between 0x10 and 0x02 and the result will be 0x0C stored in WREG as ‘d’ is mentioned as zero.

27. SUBWFB f,d,a

Description : Subracts WREG from the value at the location mentioned by file register ‘f’ with borrow. The flags affected are C, DC, OV, Z and N.

Ex. SUBWFB 0x45,0,0 ; Assume the value of WREG is 0x02 and value at 0x45H is 0x10

After executing this instruction the result is the difference between 0x10 and 0x02 and the result will be 0x0C stored in WREG as ‘d’ is mentioned as zero.

28. SUBWF f,d,a

Description : Subtracts WREG from register file ‘f’ and puts the value back in ‘f’ or WREG depending upon the value of ‘d’. The flags affected are C, DC, OV, Z and N. In this instruction, no borrow is used.

29. SWAPF f,d,a

Description : Swaps the nibbles in f. The lower nibbles are swapped with upper nibbles. A nibble is a group of 4 bits. None of the flags are affected by this instruction.

Ex. SWAPF 0x5A,1,0 ; Assume value 0x AB at location 0x5A.

The instruction swaps the nibbles of 0xAB and the resulting value 0xBA is put back at location 0x5A as value of ‘d’ is 1.

30. TSTFSZ f,a

Description : Tests the value at register file ‘f’ and skips if its zero. None of the flags are affected by this instruction.

31. XORWF f,d,a

Description : Performs exclusive OR with WREG and register file given by ‘f’. The flags affected are Z and N.

These are the byte oriented instructions in PIC 18 F series microcontroller. Our next section is dealing with bit oriented instructions. With these instructions we can manipulate each byte , bit by bit. There are 5 bit oriented file register operations.

Bit Oriented File Register Operations

None of the status flags are affected in these 5 bit oriented operations.

32. BCF f,b,a

Description : Clears the bit in register file ‘f’ given by the bit position ‘b’. Tha value of b varies from 0 to 7.

Ex. BCF 0x03,2,0 ; Suppose value at 0x03 is FF H

This instruction clears the 2nd bit in the value FF H. So the result will be FB H. That is 2nd bit is cleared as per the instruction.

33. BSF f,b,a

Description : Sets the bit in register file ‘f’ given by the bit position ‘b’. Tha value of b varies from 0 to 7.

Ex. BSF 0x03,2,0 ; Suppose value at 0x03 is 00 H

This instruction sets the 2nd bit in the value 00 H. So the result will be 04 H. That is 2nd bit is set as per the instruction.

34. BTFSC f,b,a

Description : Test the bit position ‘b’ in the register file ‘f’ and if its zero, then the next instruction is skipped.

Ex. BTFSC 0x05,1,0

This instruction checks the 1st bit position is cleared of set. If its is cleared, then the next instruction is skipped.

35. BTFSS f,b,a

Description : Test the bit position ‘b’ in the register file ‘f’ and if its set, then the next instruction is skipped.

Ex. BTFSS 0x04,2,0 ; Assume the value at 0x04 H is 0x04 H.

After executing BTFSS, the next instruction will be skipped as 2nd bit in the register file 0x04 is set.

36. BTG f,b,a

Description : Toggles the bit position ‘b’ in the register file ‘f’.
Ex. BTG 0x08,2,0

This instruction toggles the 2nd bit of the value at the location given by 0x08.
Control Operation

The PIC 18F series microcontroller has got around 25 control instructions.

37. BC n

Description: Branch if Carry . If the Carry bit is ’1’, then the program will branch. The 2’s complement number ’2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. The value of ‘n’ varies from -128 to +127.

Ex. BC 5

If carry is 1 and PC is 0x10. Then after the instruction, PC will point to 0x10 + 2s complement of 5 + 2. That is,PC will now have the value 0x10 + 0x12.

38. BN n

Description : If the Carry bit is ’1’, then the program will branch. The 2’s complement number ’2n’ is
added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

39. BNC n

Description : Branch if no carry. Exactly opposite of BC n.

40. BNN n
Description : Branch if not negative. Exactly opposite of BN n.

41. BNOV n

Description : If the overflow bit is zero, then the program will branch. The 2’s complement number ’2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

42. BOV n

Description: Branch if overflow bit is set. Exactly opposite of BNOV n.

43. BNZ n

Description : Branch if not zero. If the zero bit is zero, then the program will branch. The 2’s complement number ’2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

44. BZ n

Description : Branch if Zero. Exactly opposite of BNZ n.

45. BRA n

Description : Branch Unconditionally. The value of n varies from -1034 to 1023. The 2’s complement number ’2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

46. CALL k, s

Description : Subroutine call of entire 2 Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If ’s’ = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then, the 20-bit value ’k’ is loaded into PC<20:1>. CALL is a two-cycle instruction.

The value of k varies between 0 < k < 1048575.

47. CLRWDT

Description : CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set.

48. GOTO n

Description : GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range. The 20-bit value ’k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction. The value of n varies from 0 < k < 1048575.

49. NOP

Description : No operation performed in this single cycle operation.

50. RETRUN s

Description : Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default).

51. RETLW k

Description : Return with literal in k. The value of k varies from 0 < k < 255.

52. RESET

Description : This intruction resets all flags and registers which are affected by MCLR Reset.

53. RETFIE s

Description : Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default).

54. PUSH

Description : The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows to implement a software stack by modifying TOS, then push it onto the return stack.

55. POP

Description : The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack.

56. DAW

Description : DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result.

57. RCALL n

Description : Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2’s complement number ’2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the address will be PC+2+2n. This instruction is a two-cycle instruction. The value of n varies from -1024 n 1023.

58. SLEEP

Description : The power-down status bit (PD) is cleared. The time-out status bit (TO) is set.Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.



Literal Operations

59. ADDLW k

Description : The contents of W are added to the 8-bit literal 'k' and the result is placed in W. The value of k varies between 0 < k < 255. All the status flags are affected by this instruction.

60. ANDLW k

Description : The contents of W are AND ed to the 8-bit literal 'k' and the result is placed in W. The value of k varies between 0 < k < 255. The status flag affected are Z and N.

61. IORLW k

Description: The contents of working register WREG is done inclusive-OR with literal k. And the result is placed in W. The status flag affected are Z and N.

62. MOVLW k

Description : The literal k is loaded into working register W. None of the status flags are affected.

63. MULLW k

Description : The contents of the working register W is multiplied with literal k and the result is placed in PRODH and PRODL.

64. SUBLW k

Description : The contents of working register W is subtracted from literal k. All status flags are affected by this instruction.

65. XORLW k

Description : The contents of the working regsister W is exclusive-OR with literal k. The flags affected are Z and N.

66. MOVLB k

Description : This loads the Bank Select Register BSR < 3:0>. None of the status flags are affected by this instruction.