Input Output PORTS

Input and Output PORTS

For communicating with the outside world, PIC18F452 microcontroller is provided with 5 ports divided into :- PORTA, PORTB, PORTC, PORTD and PORTE. Some pins of I/O ports are multiplexed with alternate functions like SPI, USART, ADC, CCP, PWM etc. In general, when a peripheral function is enabled, then the corresponding pin cannot be used a I/O pins.

Each port has three registers for its operation. These registers are :

1. TRIS register ( Data Direction Register )

2. PORT register ( Reads the level of the pins 0 or 1 )

3. LAT register ( Output Latch )

PORTA:

PORTA is a 7 – bit wide bi-directional port with corresponding data direction register TRISA.Setting TRISA bits = 1, makes the corresponding PORT A pin as input . This will drive the corresponding output driver in high impedance state. Clearing the TRISA bits will make the pins as output and put the content of the output latch to the corresponding pin.

Reading PORTA register will read the status of the pin, whereas writing to PORTA register will write to the latch and not to the PORTA pins. This is a major difference between write and read operations on port pins.The Data Latch Register LATA is also memory mapped, and writing to LATA register is same as PORTA register. There is no diffference between the two operations. Both are same and permitted. On Power On Reset (POR) the pins RA5, RA3, RA2, RA1 and RA0 are configured as digital outputs, whereas RA6 and RA4 are configured as digital inputs.

Example Code 1 :

MOLW 0x00,0;

MOVWF TRISA,0; Clearing TRISA, making it as output

MOVLW 0xFF,0;

MOVWF PORTA, 0; Writing to PORTA, making all pins HIGH

MOVLW, 0x0F,0;

MOVLW LATA, 0; Writing to PORTA, making lower 4 pins HIGH

The PORTA pins are multiplexed with Timer0 function, OSC2 pins and ADC function.

PORTB :

PORTB is a 8 – bit wide bi-directional register with corresponding data direction register TRISB.On Power On Resets ( POR ), all the 8 pins of PORTB are configured as inputs.Each of the PORTB pins has a weak internal pull-up.This is performed by clearing RBPU (INTCON2<7>). The weak pull up is automatically turned off, when the port pin is configured as digital output. The pull ups are disabled on POR. For of the PORTB pins, RB7 : RB4, have an interrupt on change feature.Only pins configured as an input can cause this interrupt to occur. The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF. RB5 pin can no longer be used as a general purpose I/O pin, and should be held low during normal operation to protect against inadvertent ICSP mode entry.

Example Code 2:

CLRF TRISB; Configuring PORTB as output

MOVLW 0xF0,0;

MOVWF LATB,0; Making RB7 : RB4 as High

PORTC :

PORTC is a 8 – bit wide bi-directional register with corresponding data direction register TRISC.On Power On Resets ( POR ), all the 8 pins of PORTC are configured as inputs. The PORTC pin is multiplexed with several peripheral functions like schmitt trigger input, I2C and SPI. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

Example Code 3 :

MOLW 0x00,0;

MOVWF TRISC,0; Clearing TRISA, making it as output

MOVLW 0xFF,0;

MOVWF PORTC, 0; Writing to PORTA, making all pins HIGH

MOVLW, 0x0F,0;

MOVLW LATC, 0; Writing to PORTA, making lower 4 pins HIGH

PORTD :

PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode).

Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. On a Power-on Reset, these pins are configured as analog inputs.

PORTE :

PORTE is a 3-bit wide, bi-directional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode).

Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register reads and writes the latched output value for PORTE. PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. On a Power-on Reset, these pins are configured as analog inputs.