JTAG Debugger

JTAG - Debugger

JTAG (Joint Test Action Group , pronounced as “jay-tag”) is an IEEE specification ( IEEE 1149.1). It is actually a methold for doing full chip testing and was orginally implemented to allow testing of all the pin connections of a chip and its interconnections to other chips on the circuit board. It is a serial protocol and chips on the board may be daisy-chained together. In simple terms, the JTAG serial chain through the chip may be wired through any on chip devices but typically minimally connects to all the Input-Output pins and buffers. The chain may be several score long or thousands of elements. There is no specification stating any inclusion of resources for software debug nor is there is a prohibition.

Different processors implement OCD via JTAG in different ways. The 600 series of PowerPC microprocessors purely use the hardware test chain which winds its way through many of the on-chip resources. Somewhere in the multi-thousand stage serial chain is the instruction register, for example. Debugging with this system is tedious since each core OCD action may take many trips through the entite JTAG chain. Although the debugger may only be interested in a 32 bit piece of the chain, all elements must be traversed, and multiple times. Downloading user code may be as slow as less than one hundred bytes per second.

Another drawback to implement that use a shared hardware/software debug chain ( TI DSP chips, 600 family PowerPC, etc ) is the way the chain is routed during chip design. Since this is typically the least critical path and the least critical part of the chip design/layout, the designers let the silicon auto-router layout the chain’s pathway after the rest of the chip has been laid out. This means that each revision of the silicon may have a different JTAG chain; hence the host debugger software must be aware of every revision of silicon. TI solves this problem by often updating their OEM emulator software kit. This does not help the end user unless he had a very reliable debugger vendor.

An alternative methold to the JTAG OCD is to use a different chain via the JTAG port. This is allowed for in the IEEE specification. Using this methold, one chain is available for the hardware test and debug of the chip, another for software debug. This methold is used in the IBM 400 series of PowerPC as well as in the SHARC DSP from Analog Devices. This secondary chain allows access to debug specific registers, usually only two or three are needed. In the IBM chips, the debug port has access to an instruction stuff buffer, a debug control register and a debug status regitser. The instruction stuff buffer allows the debugger to stuff any opcode into the core processor’s instruction register, in effect causing a single step to occur. By executing the proper instructions, any action needed may be performed. The debug control and status rgisters allow for the typical debug commands such as single step and run.

An advantage to using the JTAG port for software debug is that it does not need any additional pins on the processor for seperate hardware and software debug. A disadvantage is the added overhead needed for each basic action.